TSV Board Level Reliability
Through silicon vias (TSV) offer a potential solution to addressing some of the interconnect issues that impact the CPU-Memory latency bottle neck. This project focuses on how TSVs can be adopted for this purpose and evaluates the challenges to applying this technology in future packaging solutions. Possible exploration areas might include reliability of TSV interconnect, road mapping, fabrication of high density TSV, and/or design tools.
If you are interested in participating in this project:
Members - Go to the "Subscribe Here" section to the right and select the "Subscribe to space" key.
Non Members - Go to the "Contact" section to the right and select the "Contact project facilitator" key.