TSV Signal Integrity

TSV (Through-Silicon Vias) Signal Integrity Project:  (Lead: NIST)
This project was initiated as an evaluation of the status of TSV, and during that evaluation, identified some potential avenues of exploration for HDP User Group. The Signal Integrity project was first proposed in February 2014, entered the Definition Phase in June 2014, and was concluded in April 2016.  The approach here was to generate an experimental project to compare the signal quality of TSV packaging to traditional packaging. 
This empirical approach required the procurement of hardware which to-date has not been made available for non-proprietary experimentation. 
Benefits of the Project:
To conclude this project, Yaw Obeng and Dave Love wrote up a short review, summarizing of the current status of the public knowledge of TSV signal integrity. This summary can be found on the HDPUG.org website in the Projects section. In that document, there are 14 references to published work on the topic.
Project stage: 
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Lead company: 
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Idea Information


3D system integration is one of the most important strategic key technologies in microelectronic packaging and system integration worldwide. With 3D wafer level system integration technologies, multiple electronic devices such as sensors, processors, memories, transceivers, can be integrated heterogeneously into one wafer level system-in-package (WL-SiP). The heterogeneous wafer level integration approach has specific advantages in terms of electrical performance, form factor and manufacturing cost. Through Silicon Vias (TSVs) is a key component of implementing 3D packaging.  Already used extensively in high volume image sensors the technology is now seen as a potential solution to addressing some of the interconnect issues that impact the CPU-Memory latency bottle neck.  A range of fabrication solutions are now under development, that are providing designers with future options to interconnect on both sides of the silicon IC.  This helps to reduce interconnect lengths and potentially provides solutions for more efficient routing.



This project is being led by Yaw Obeng, PhD. Dr. Obeng is a Senior Scientist in the Center for Nanoelectronics Device Reliability at NIST. A profile and contact information for Dr. Obeng can be found here:  http://www.nist.gov/pml/div683/grp06/yobeng.cfm


Designers of compute and network systems are increasingly faced with the challenge of latency between CPU chip and cache memory to meet the demands of latest generation processor cores. Packaging technology can ease this problem by decreasing the distance from CPU to memory.

The use of 3D TSV technology can potentially address the proximity issue by mounting the memory (stack) on the back of the CPU chip or alternatively face to face with a silicon interposer providing the interconnect medium between them.

2.5D Technology is a more achievable solution in the immediate timeframe. In this case, the TSVs are in a silicon (or glass) interposer to allow the construction of a horizontal MCM with very tight spacing between CPU and memory.

A hybrid of both techniques is called "5.5D" and consists of memory chip stacks (3D) mounted on interposers with CPU and other devices (2.5D).

To date TSV processing  is in its infancy and numerous challenges have to be overcome before it can be used to facilitate the potential solution discussed. The project is therefore intended to conduct a preliminary feasibility study on the suitability and maturity of TSV technology as a solution to the increasingly looming CPU to memory latency issue.

Two areas of research collaboration have been identified:

1. Comparison of signal integrity (bit error rate, eye diagrams, s-parameters) between 2.5D packaging and traditional packages mounted on PCB.

2. Evaluation of reliability of the delicate TSV structures while the 2.5D or 3D package is mounted on a PCB, with all the inherent strains imposed by attaching a package with its inherent coplanarity to a stiff network or server board. 

Definition Information


Proposed deliverables of project: 

1. Determine Reliability of TSV structures and packaging after board-level assembly. Post Assembly testing has proven more stressful than standard component testing. Low K dielectrics and TSV's are especially fragile. This will allow each system integrator to assess how this type of device will perform in their customers use environment.

2. Develop SMTA guidelines documentation for optimized assembly process of this new package type. Include SMTA characterization study (cross sections, profiles, etc.)

3. Explore a new RF-based TSV resistance test procedure that has been developed by NIST. This new method will help improve the sensitivity of the reliability assessment of the technology in this category of devices and may become an important tool for EMS providers in implementing 3D technologies.

4. Thermal transfer properties of 3D structures using TSV needs to be explored. It is known that integration through die stacking impedes thermal dissipation. Tests in this area will help system houses with establishing design guidelines for TSV technology devices.

5. Compare signal integrity of 2.5D and 3D memory buses to traditional package-on-PCB assembly.  Answer questions such as "do we need differentail pair in closely coupled short-throw I/O on 2.5D substrates?"  Outputs will be bit error rates, eye diagrams, and s-parameters.

A forum to share information on subjects related to TSV technology, and it is reached by clicking on the “Project Discussion” link in the Content Sections menu on the right hand side of the project web page.

Key Participants: 
Park Electrochemical
TTM Technologies