Current projects

Project type: Lead-Free
Project stage
Harsh Use Environment Alloy Evaluation

This project proposes to evaluate lead free solders that may be suitable for harsher environmental and use conditions such as transportation, and defense applications.

Definition
SAC Aging 3

The aim of the SAC Aging 3 project is to use the Alloy Common Test Vehicle and to perform baseline microstructural characterization on ambient aged and elevated temperature isothermally aged samples.  In addition, it will perform failure mode analysis and characterization of ATC samples to determine extent of microstructural evolution and impact on final failure. At the same time the project will thermal cycle additional non-monitored samples for microstructural analysis at different thermal aging times and temperatures.  Data collected from the HDP User Group SAC Aging 2 project will be used for a comparison.  However, because of the Warped PWBs used in that project, some data cannot be used and/or can only be used with suspect.  Data from various projects using the same Alloy Common Test Vehicle will be compared for ultimate understanding.

Implementation
Lead Free PWB Materials Reliability Phase 5

Phase 5 of the Lead-Free PWB materials reliability program will evaluate selected latest generation PWB laminates. The testing program will include thermal analysis and stress testing, thermal cycling endurance, susceptibility to CAF and evaluation of electrical characteristics at high frequencies using a new connectorless SPP (short pulse propagation) design. Properties will be evaluated both before and after multiple simulated reflow conditions.

 

Implementation
Mini Power Cycles
Network capabilities must now accommodate increasing demands for data transmission from business and consumer customer bases over fixed access and wireless networks at any time of day or night. These high traffic operational modes, coupled with energy saving modes at the component level, have the potential to induce new reliability challenges by adding new types of thermomechanical stress and strain to equipment. Rapid and frequent mini-power cycling is now being coupled with the well-known stress from diurnal cycling and typical thermal operating conditions. Network operations have long avoided traditional power cycling because power cycles are known to degrade solder joint performance and reduce the life and performance of hardware. The advent of Sn-based, Pb-free alloys for solder assembly is expected to increase susceptibility to power cycling-induced damage.
 
Implementation
Project type: Opto-Electronics
Project stage
Optoelectronics II

Phase 2 of the HDP optoelectronic will demonstrate how the trends in bandwidth and speed to design for next generation systems will be fulfilled through optical waveguide technology. Phase 2 will bring a practical perspective to optoelectronics by building a prototype system level demonstration vehicle . This pseudo system will have physical attributes found in today’s systems such as: routers, switches, and storage systems. Its’ design will rely on photonic components to solve many limitations of electrical interfaces. The channels will be a mix of polymer waveguides and fibers to enable high bandwidth per link at speeds exceeding 50 Gb/s per channel. The pseudo system will be composed of  linecards that will be inserted into a  “slot chassis” type of architecture to mimic today’s systems. These linecards will be interconnected using optical links and transmit and receive high bandwidth and high speed signals through an optical backplane.

Implementation
Project type: Printed Wiring Board Technology
Project stage
Better CAF Acceleration Equation

Classic CAF (Conductive Anodic Filamentation) is a two-step process, firstly the creation of a pathway by hydrolysis followed by electrochemical filament growth. Where there is no pathway there can be no CAF, hence existing acceleration factor equations which model the process as a single step are clearly incorrect. The project will determine a better acceleration factor equation for CAF and quantify the effects of Voltage, Temperature and Humidity hopefully enabling shorter testing time for CAF material qualification.

Idea
PWB Environmental Life Cycle Analysis 2

Phase 1 of the PWB Environmental Life Cycle Analysis project focussed on developing a calculator to estimate green house emissions associated with fabrication of printed wiring boards. Data for this phase of the project was collected from two fabrication plants, one specializing in conventional multi-layer circuit boards and the other specifically set up to manufacture high density interconnect (sequential build-up) designs. Phase 2 of the project aims to extend the calculator so that it is adaptable to other fabrication plants and can also be used for non-standard designs. In addtion the team are looking to partner with other organizations to consolidate on process data collection.

Implementation
CAF TV for Material Characterization

CAF (Conductive Anodic Filamentation) is normally characterized as an effect subject to the influences of design, process and materials. This adds complication to product development for laminate manufactures as lengthy failure analysis is normally required when CAF testing is performed using standard test vehicles. The project aim is to develop a test vehicle that will allow performance evaluation to be limited to laminate material only, thus eliminating the variables of design and process. It is expected that the project will lead to more focused and quicker laminate testing and development for CAF resistance.

Idea
Design Related PWB Material Damage

Previous results from the Pb-Free PWB materials reliability project have indicated that for the MRT test board used there is a clear relationship between design features and the increased risk of material delamination through SMT reflow. Using modified design variants of the MRT test board, this project explores further the impact of reduced through hole via pitch and hole wall to hole wall spacing, board thickness, number of layers and position of power distribution planes on the occurrence of post SMT assembly material damage.

Implementation
PTH Creep Fatigue Under Roughness Influence

In the previous project "PTH Lifetime Predictor for TC", the lifetime predictor derived is applicable only when the strain is greater than 3.0x10-4 . Below this level, the strain is mainly creep strain which does not obey the Manson-Coffin rule. This project serves to provide a better understanding of creep strain on PTH and the influence of Cu plating roughness, using FEM simulations and verifying through high temperature testing. Once the creep characteristics of a typical PWB copper plating are identified, the creep consideration can be added into the AF equation of the PTH lifetime predictor.

 

Idea
Board Thickness Effect on ATC Reliability

The purpose of this project is to determine the effect of varying board thickness on the solder joint reliability (SJR) of a variety of devices that are attached to those boards. Opinions, modeling results, and data on this topic are conflicting. There have been no definitive studies published.

Implementation
Electro-Chemical Migration 2

In our previous project Electro-Chemical Migration we found that a No Clean Flux, which is designed to leave a benign residue, can result in crevice and pitting corrosion. We also discovered the flux activators can remain on the board due to excessive flux or entrapment (ie,: Selective solder fixtures, Wicking into soldermask and Non solder mask defined pads).  We already knew that harsh environments subjects devices to high humidity.  This all means that Ions can be mobilized and cause corrosion on exposed copper features.  In this follow-on project we would like to develop a Test Method for determining Pitting / Crevice Corrosion capability of a Solder Flux. We then would submit the method to IPC Cleaning and Coating Committee for consideration of an additional test within J-STD 004 to evaluate flux potential to propagate Pitting / Crevice Corrosion capability of a Solder Flux on Cu and Sn and subsequently work with the IPC Committee on Cleanings and Coatings to implement our recommendations.

Definition
Pad Cratering

Lead-free (LF) solder joints are stiffer than tin-lead solder joints, and LF compatible (Phenolic-cured) PCB dielectric materials are more brittle than the FR4 (dicy-cured) equivalent. These two factors, coupled with the higher peak reflow temperatures used for lead-free assemblies, could transfer more strain to the PCB dielectric structure, causing a cohesive failure underneath BGA corner pads. This project will examine the phenomenon with the goal of determining test and screening methods.

Implementation
PWB Back Drilling Phase 2


 Phase 1 of the project showed that the shallow back-drill fails earlier relative to the medium and deep back-drill and proved the capability to electrically measure remaining stub lengths from a single ended trace on a single inner layer position.  Phase 2 will focus on the shallow back-drill but on a much thicker 30 layer PCB using two heating circuits and will evaluate the capability to electrically measure via stubs from various layers within the 30 layer PCB TV using differential signal traces.

Implementation
Multiple Lamination

As BGA pitch decreases and I/O count increases, stacked microvia designs become more prevalent However, there is little data in the public domain on the reliability of these stacked designs. Previous studies done by PWB Interconnect Solutions and EIT showed that there can be a significant reliability degradation of stacked microvias in certain constructions. This project is designed to evaluate 2, 3, and 4 stack microvias both “stand alone” and stacked on buried via  and compare the data to a plated through holes (PTH) using Interconnect Stress Testing (IST) and TMA/DMA/TGA testing.  The test vehicle will consist of three different thicknesses (.062, .093, and .125) with two different laminate materials and will simulate 0.8/0.4mm and 1.0/0.5mm BGA pitches. The extended process time at high temperatures in multiple lamination designs coupled with multiple assembly cycles and rework cycles may cause stress that are undocumented. Participants in this project will receive statistically accurate data on stacked HDI reliability.

Implementation
Ultra-Thin HDI Multi-Purpose Test Vehicle

As the electronics market is driven more and more by smartphones and notebooks, the rigid boards become smaller and thinner which only amplifies the lag between the current process methods/test vehicles and the design capabilities. This gap presently is as much as a decade behind.  As the gap grows, the older test vehicles become obsolete and are no longer applicable.  Each new product requires a unique test vehicle and modified process methods.  This engineering effort drives delays in production and manifests itself in increase costs for both OEM and suppliers.
The process methods used along with the current test vehicles used, do not capture interconnect density or thinness, they miss potential failure mechanisms (e.g., ion migration). In addition, the low density patterns introduce artifacts not seen in production before (e.g., distortion of via stack).  The test parameters may exceed practical limits of design or are inappropriate to application (e.g., 50V CAF).

As a result there is an increasing abandonment by the OEMs in favor of non-standardized “end product” test vehicles.  This only widens the gap between up-stream development & down-stream practice.  The only resolution is that the problem must be solved by the component, PCB & material supply-chain companies, because the OEMs are working in a black box.

 

Implementation
Digital Image Speckle Correlation 2

This project will be a continuation of the DISC Project, using additional stackups from the recently completed Multi-lam project. The Team will expand the scope of structures to include 2-4 stack on 12, 18 and 24 Layer PWBs to test repeatability of the Digital Speckle method. This project creates and compares empirical data used in available FEM tools such as CALCE, Sherlock, etc.

Idea
Military Halogen Free Laminate Evaluation

HDP has completed several projects evaluating lead free laminates using general commercial specifications and criteria. This project will evaluate PCB laminate materials using military/aerospace specifications and criteria.

Idea
Project type: Emerging Technology
Project stage
Future HDI

BGA pitch is moving steadily downward and high I/O BGAs are common at 1mm and 0.8mm pitch today and starting to appear at 0.65mm pitch. Consumer PCB’s (smart phone, tablet, etc.) have already moved to large I/O BGA’s at 0.5 and even 0.4mm pitch. This technology density is often supported by “Any Layer/Every Layer HDI PCB’s”. Generally the PCB’s used in Any Layer designs are very thin (typically 0.8mm thick or less). Participants in this project will determine the maximum PCB thickness that can be supported with “Any Layer” designs. The uniqueness of this project is the project is a new construction concept merging aspects of today’s high end telecom/computer designs with aspects of consumer PCB’s. There is no other similar project known to have been proposed or completed.

 

Implementation
Project type: Printed Wiring Board Assembly
Project stage
Solder Joint Reliability with Surface Finishes

This project serves to evaluate the toughness of solder joints on boards, coated with various surface finishes, and assembled with large components and fine-pitch components using different solder alloys. The assembled boards will go through thermal cycling, bending (optional) and drop tests with the results analysed to find the effects the various surface finishes have on solder joints formed with various solder alloys.

Definition
Low Ag Alloy Solder Paste Reliability

 

Phase 1 process feasibility study of low Ag alloy solder paste showed that the candidate materials tested can be used in the process without major assembly defects. Phase 2 will evaluate the reliability of these solderpaste. Phase 2 Reliability is a 2 leg project. The first leg will assemble and test a QFN component to down select alloys for next BGA leg. Leg 2 will assemble and test a BGA component with a SAC305 solder ball and the various candidate solderpaste.

 

 

Implementation
Press-Fit Technology

More and more products use electronic devices to communicate, in 2020 it is expected that there will be more than 50 billion connected devices in the world. This means that many electronic products, especially mobile base stations and core network nodes, need to handle enormous amount of data per second. One important link in this communication chain are high speed press fit connectors that are often used to connect mother boards and back planes in core network nodes. These new high speed press fit connectors have several hundred thin, short and frail pins that easily could be damaged if not produced and handled correctly. Figure 35 shows a high speed press fit connector. These new connectors are very expensive and small variations in via hole dimensions and hole plating thickness will affect the connections for these sensitive press fit pins. If the holes are too small, the pins will bend.  If the holes are too big, they will not form a gas tight connection.

Implementation
Component Rework Reliability

Current rework guidelines regarding the number of allowable reworks for a component site are inadequate and need to be upgraded or better understood with solid research.  This project proposes to establish a limit for the number of reworks that can occur for components or particular component types on an assembly without impacting the overall reliability. The project will develop new guidelines for reworks to be used in PWA and will write a proposal for new specifications on rework of PWA which will be delivered to standards bodies for their consideration.

Implementation
RF Failure Detection

RF measurements of signal paths are far more sensitive to incipient circuit (or solder joint) failure than our standard resistance measurements or event detectors. This project will use Accelerated Temp Cycle testing to compare RF measurement to DC measurement failure distributions in solder joint reliability testing. The project will determine if RF measurement of signal loss is a useful criterion for failure. The project may also compare RF measurement to event detection.

Idea
Project type: Component Packaging
Project stage
FCBGA Package Warpage 2

Warpage is an assembly manufacturing problem resulting in opens, weak joints, Head on Pillow (HOP) and None Wet Open (NWO) defects. With the IC's becoming increasingly thinner, the silicon has less ability to resist deformation of the component package. This deformation combined with short IC leads and a very flexible substrate often exceeds the termination-to-solder paste gap.  The net result is that warpage will become an increasing problem in the future.  Warpage as a result of the thickness of the IC's used,along with defects such as open joints or very weak joints can be caused by short leads on the IC's combined with very flexible carriers. This combination will most likely cause interconnections that will be poorly made or never made  In phase 2 of this project, we will characterize the newly defined process from FCBGA Package Warpage 1 and develop a consistent methodology to use in normal production.

Implementation
Project type: High Frequency
Project stage
High Frequency Flex