Current projects

Project type: Lead-Free
Project stage
SAC Aging 3

The aim of the SAC Aging 3 project is to use the Alloy Common Test Vehicle and to perform baseline microstructural characterization on ambient aged and elevated temperature isothermally aged samples.  In addition, it will perform failure mode analysis and characterization of ATC samples to determine extent of microstructural evolution and impact on final failure. At the same time the project will thermal cycle additional non-monitored samples for microstructural analysis at different thermal aging times and temperatures.  Data collected from the HDP User Group SAC Aging 2 project will be used for a comparison.  However, because of the Warped PWBs used in that project, some data cannot be used and/or can only be used with suspect.  Data from various projects using the same Alloy Common Test Vehicle will be compared for ultimate understanding.

Implementation
Harsh Use Environment Alloy Evaluation

This project proposes to evaluate lead free solders that may be suitable for harsher environmental and use conditions such as transportation, and defense applications.

Definition
Lead Free PWB Materials Reliability Phase 5

Phase 5 of the Lead-Free PWB materials reliability program will evaluate selected latest generation PWB laminates. The testing program will include thermal analysis and stress testing, thermal cycling endurance, susceptibility to CAF and evaluation of electrical characteristics at high frequencies using a new connectorless SPP (short pulse propagation) design. Properties will be evaluated both before and after multiple simulated reflow conditions.

 

Implementation
Mini Power Cycles
Network capabilities must now accommodate increasing demands for data transmission from business and consumer customer bases over fixed access and wireless networks at any time of day or night. These high traffic operational modes, coupled with energy saving modes at the component level, have the potential to induce new reliability challenges by adding new types of thermomechanical stress and strain to equipment. Rapid and frequent mini-power cycling is now being coupled with the well-known stress from diurnal cycling and typical thermal operating conditions. Network operations have long avoided traditional power cycling because power cycles are known to degrade solder joint performance and reduce the life and performance of hardware. The advent of Sn-based, Pb-free alloys for solder assembly is expected to increase susceptibility to power cycling-induced damage.
 
Implementation
Project type: Opto-Electronics
Project stage
Optoelectronics II

Phase 2 of the HDP optoelectronic is a demonstrator.  The project is designed to show the trends in bandwidth and speed may be implemented in an electro/optical environment. Several different waveguide technologies are evaluated in the project, using a prototype system level demonstration vehicle. The demonstrator has physical attributes found in today’s systems such as: routers, switches, and storage systems. Its’ design rely s on photonic components to solve many limitations of electrical interfaces.

The channels are a mix of polymer waveguides and fibers to enable high bandwidth per link at speeds exceeding 40  Gb/s per channel. The pseudo system is composed of  line cards that will be inserted into a  “slot chassis” type of architecture to mimic today’s systems. These line cards are interconnected using optical links and transmit and receive high bandwidth and high speed signals through an optical backplane.

 

Implementation
Project type: Printed Wiring Board Technology
Project stage
PWB Environmental Life Cycle Analysis 2

 

Building on the results from phase 1 of the project the Phase 2 will develop a more flexible PWB fabrication Green House Gas (GHG) emissions calculator. It will have added capability to support advanced/emerging PWB materials. Phase 2 will also raise greater industry awareness of the project and engage with other organizations / companies. We will also increase industry awareness by external publication.

 

Implementation
Design Related PWB Material Damage

Previous results from the Pb-Free PWB materials reliability project have indicated that for the MRT test board used there is a clear relationship between design features and the increased risk of material delamination through SMT reflow. Using modified design variants of the MRT test board, this project explores further the impact of reduced through hole via pitch and hole wall to hole wall spacing, board thickness, number of layers and position of power distribution planes on the occurrence of post SMT assembly material damage.

Implementation
Digital Image Speckle Correlation 2

Digital Image Speckle Correlation 2

This project is a continuation of the DSC Project, using additional stackups from the recently completed Multi-lam project. The Team expands the scope of investigated structures to include 2-4 stack on 12, 18 and 24 Layer PWBs to test repeatability of the Digital Speckle method. This project creates and compares empirical data used in available FEM tools such as ANSYS, Sherlock, etc. The resultant data is used to create a model that predicts reliability for on and off-stack buried structures, advancing the State of the Art both as a reliability prediction method and as an evaluation of design trade-offs. The Digital Speckle method is much quicker than the other tools because it does not require ATC testing, which can take months.

 

 

Idea
Board Thickness Effect on ATC Reliability

The purpose of this project is to determine the effect of varying board thickness on the solder joint reliability (SJR) of a variety of devices that are attached to those boards. Opinions, modeling results, and data on this topic are conflicting. There have been no definitive studies published.

Implementation
Military Halogen Free Laminate Evaluation

HDP has completed several projects evaluating lead free laminates using general commercial specifications and criteria.

 

Materials used in Electronic Products are getting more and more scrutiny by government agencies around the globe (RoHS, REACH, CA Prop 65 etc). To date the U.S. Military has not shown a strong interest in halogen free laminate. However some military analysts feel there is a need to understand if halogen free laminates can withstand the more rigorous military testing criteria. This project will evaluate several laminates using military / aerospace reliability testing criteria.

 

Idea
Electro-Chemical Migration 2

In our previous project Electro-Chemical Migration we found that a No Clean Flux, which is designed to leave a benign residue, can result in crevice and pitting corrosion. We also discovered the flux activators can remain on the board due to excessive flux or entrapment (ie,: Selective solder fixtures, Wicking into soldermask and Non solder mask defined pads).  We already knew that harsh environments subjects devices to high humidity.  This all means that Ions can be mobilized and cause corrosion on exposed copper features.  In this follow-on project we would like to develop a Test Method for determining Pitting / Crevice Corrosion capability of a Solder Flux. We then would submit the method to IPC Cleaning and Coating Committee for consideration of an additional test within J-STD 004 to evaluate flux potential to propagate Pitting / Crevice Corrosion capability of a Solder Flux on Cu and Sn and subsequently work with the IPC Committee on Cleanings and Coatings to implement our recommendations.

Definition
Better CAF Acceleration Equation

Classic CAF (Conductive Anodic Filamentation) is a two-step process, firstly the creation of a pathway by hydrolysis followed by electrochemical filament growth. Where there is no pathway there can be no CAF, hence existing acceleration factor equations which model the process as a single step are clearly incorrect. The project will determine a better acceleration factor equation for CAF and quantify the effects of voltage, temperature and humidity hopefully enabling shorter testing time for CAF material qualification.

Definition
PWB Back Drilling Phase 2


 Phase 1 of the project showed that the shallow back-drill fails earlier relative to the medium and deep back-drill and proved the capability to electrically measure remaining stub lengths from a single ended trace on a single inner layer position.  Phase 2 will focus on the shallow back-drill but on a much thicker 30 layer PCB using two heating circuits and will evaluate the capability to electrically measure via stubs from various layers within the 30 layer PCB TV using differential signal traces.

Implementation
CAF TV for Material Characterization

CAF (Conductive Anodic Filamentation) is normally characterized as an effect subject to the influences of design, process and materials. This adds complication to product development for laminate manufactures as lengthy failure analysis is normally required when CAF testing is performed using standard test vehicles. The project aim is to develop a test vehicle that will allow performance evaluation to be limited to laminate material only, thus eliminating the variables of design and process. It is expected that the project will lead to more focused and quicker laminate testing and development for CAF resistance.

Definition
PTH Creep Fatigue Under Roughness Influence

In the previous project "PTH Lifetime Predictor for TC", the lifetime predictor derived is applicable only when the strain is greater than 3.0x10-4. Below this level, the strain is mainly creep strain which does not obey the Manson-Coffin rule. This project serves to provide a better understanding of creep strain on PTH and the influence of copper plating roughness, using FEM simulations and verifying through high temperature (HT) testing. Once the creep characteristics of a typical PWB copper plating are identified, the creep consideration can be added into the AF equation of the PTH lifetime predictor.

 

Definition
Project type: Emerging Technology
Project stage
Future HDI

BGA pitch is moving steadily downward and high I/O BGAs are common at 1.0mm and 0.8mm pitch and starting to appear at 0.65mm pitch. Consumer PCB’s (smart phone, tablet, etc.) have already moved to large I/O BGA’s at 0.5mm and even 0.4mm pitch. This technology density is often supported by “Any Layer/Every Layer HDI PCB’s”. Generally the PCB’s used in Any Layer designs are very thin (typically 0.8mm thick or less). High density packages require 3 + stacks of microvias for routing (depending on how many I/O and design specifics) just to escape route these packages. It is inevitable that high I/O BGAs for high complexity products (Telecom, Server, etc.) will also trend downward in pitch, following the consumer trend.

 

Implementation
Project type: Printed Wiring Board Assembly
Project stage
Solder Joint Reliability with Surface Finishes

This project serves to evaluate the toughness of solder joints on boards, coated with various surface finishes, and assembled with large components and fine-pitch components using different solder alloys used in harsh-use environment. The assembled boards will go through thermal cycling and vibration tests (latter for thick boards only), and the results analysed to find the effects the various surface finishes, in both thin and thick coating, have on solder joints.

Definition
Low Ag Alloy Solder Paste Reliability

 

The Low Ag/No Process Characterization study of low Ag alloy solder paste showed that the candidate materials tested can be used in the process without major assembly defects. This project will evaluate the reliability of a selection of these solderpastes in comparison to the standard SAC305 paste for integration into a development assembly line. This is a two phase project, Phase 1 will assemble and test a QFN component to down select alloys for the following BGA Phase 2 which plans to assemble and test a BGA component with a SAC305 solder ball and the various candidate solderpaste.

 

 

Implementation
RF Failure Detection

Many transmission lines on a high speed server or network board have signal budgets of 10dB or less.  A 1 or 2 dB loss on a solder joint could result in signal integrity failures.  This is comparable to the loss typical in a well designed FCBGA package.  DC and event detectors find opens.  One of the benefits we obtained from the TSV projects is our understanding of the RF measurement technique that was pioneered at NIST.  We will attempt to use this technique where instead of using TSVs, we will use existing PCB designs and familiar components to generate a solder joint reliability study.  We will compare DC measurements to RF measurements using event detectors.

Definition
Component Rework Reliability