Completed projects

Project type: Halogen-Free
BFR/PVC Cables & Wires

A coordinated activity within the Materials/cable manufacturers/OEMs supply chain to quickly and thoroughly evaluate PVC/phthalate-free cable/wire options.  An effort like this is needed to quickly determine the best alternatives, and significantly reduce the cost and effort by the suppliers, by focusing on the specific needs of the OEMs and ODMs.  When we are finished, the users will be ready to implement the alternatives, because they have been part of the development.


Halogen-Free Assembly Reliability Phase 2

Several governments in Europe and the Far East are considering regulation to prohibit or restrict the use of certain types of substances in electronic (and other) products.  Within the marketplace, the OEM's have initiated environmentally-preferable purchasing standards that also include restrictions on the use of these substances in certain products.

In order for the electronics industry to continue its commitment to product stewardship, companies throughout the supply chain will need to understand which alternatives are available, as well as the electrical, mechanical and environmental, health and safety properties of these alternatives.

BFR/PVC Free Cables 2

This project is a follow on project to the PVC Free 1 project completed in 2011.

In project 1 we used the current industry specifications, they are for materials that do contain PVC. For this project we are considering modifying the current specifications or developing new specifications for non-PVC containing materials.

High Frequency Laminate Measurements

There is no standard platform to evaluate high frequency PWB materials, and there are several methods for measuring properties such as dielectric loss.  Furthermore, there is no definition of moisture for any of these tests and moisture can significantly change a test result.  Suppliers and OEM’s need to work together to evaluate test methods and characterize materials.

Halogen-free Guideline

Flame-retarded plastics are commonly needed to meet strict fire safety codes for electronic equipment.  Certain halogenated compounds are used as flame retardants in a variety of applications including thermoplastics, insulation materials, component mold compounds, solder masks and printed circuit board laminates.  In addition, polyvinyl chloride or PVC (a resin that contains chlorine, a halogen) is a commonly used base resin for certain cable jacketing.  However, concerns have arisen that these materials may pose certain risks to health or the environment particularly at end-of-life.

The project team will prepare a comprehensive Halogen-free Guideline.

Environmental Assessment of Halogen-free Printed Circuit Boards (DFE 2)

The HDP User Group Design for Environment (DfE) group was formed in 2002 and was represented by companies such as Dell, Ericsson, HP, IBM, Intel and Nokia. The HDP User Group released two publicly-available reports regarding key environmental attributes of electronic products. Both reports were also presented at the 2003 and 2004 IEEE International Symposium on Electronics & the Environment.

Project type: Lead-Free
Lead-Free Board Material Reliability

There are numerous laminates available to the PCB designer today. Some of these laminates have been around for a number of years and the designers and OEM's understand their capabilities and limitations. However with the advent of lead free solders and their higher processing temperatures new laminates that are designated "Lead Free Capable" are appearing. These products while tested for consumer products have not necessarily been qualified for more complex PWB designs where peak SMT reflow temperatures on the PWB surface tend to be significantly higher with the potential reulst of internal delamination. This project conducts extensive testing of a selection of latest generation laminates and pre-pregs to measure their reliability in these higher SMT reflow environments. 


This project explores whether PWB laser drilled micro-vias positioned in surface mount lands used for attachment of ball grid array components, have a negative impact on long term product reliability. Both plastic and ceramic ball grid arrays are included in the study.

SAC Aging 3

The aim of the SAC Aging 3 project is to use the Alloy Common Test Vehicle and to perform baseline microstructural characterization on ambient aged and elevated temperature isothermally aged samples.  In addition, it will perform failure mode analysis and characterization of ATC samples to determine extent of microstructural evolution and impact on final failure. At the same time the project will thermal cycle additional non-monitored samples for microstructural analysis at different thermal aging times and temperatures.  Data collected from the HDP User Group SAC Aging 2 project will be used for a comparison.  However, because of the Warped PWBs used in that project, some data cannot be used and/or can only be used with suspect.  Data from various projects using the same Alloy Common Test Vehicle will be compared for ultimate understanding.

SAC Microvoids II

Phase I of this study was a screening experiment to determine which plating and treatment parameters contribute to microvoid formation.  Phase I indicated correlations with current density, solder alloy, bath age, wetting agent, brightener content, and copper layer thickness.  There were also strong interactions of the above, all involving the wetting agent.

Lead Free Process Guideline version 3.0

The General Purpose Lead Free (GPLF) assembly system guideline was originally developed in 2004 with a minor revision added in 2005. The aim of the document was to produce a handbook that would assist system integrators/ electronics producers and their supply chain in developing Pb-Free manufacturing solutions that meet required levels of reliability while complying with forthcoming environmental legislation.  This is the next revision in that series.

Alternative Alloy Study for Hole Fill and Copper Dissolution

Investigate the damage to PWB wiring patterns caused by copper erosion in lead-free assembly. Copper erosion can occur during dipping, wave soldering and rework processes.

Lead Free PWB Materials Reliability Phase 4
Phase 4 of the Lead-Free PWB materials reliability program evaluates selected latest generation high speed PWB laminates. As with previous phases the focus will be on how the chosen materials  will perform mechanically and electrically when exposed to higher end Pb-Free surface mount reflow temperatures, typical of the conditions needed to assemble large, thick and high complexity printed circuit board designs. The testing program will monitor for any delamination issues, CAF concerns, and thermal cycling performance. Furthermore, electrical properties will be evaluated both before and after reflow. 
Lead Free Acceleration Factors

Numerous papers (Sahasrabudhe, Clech, Lau, others) indicate that ATC test conditions have a different effect on the results of SAC solder fatigue life than they do on SnPb solder fatigue life.

Multiple Alloy Screening
  • BGA suppliers have introduced a significant number of new Pb-free BGA solder ball alloys.
  • Most have been introduced to address drop/shock performance issues.
  • Very little/almost zero data is available on the thermal cycle performance of these alloys - which is key to many of the high reliability community not building hand-held consumer products.
    • The limited data available suggests that thermal cycle performance may be significantly different between the various alloys.
    • Many of these same components end up in high-reliability products.
SAC Microvoids

 This project:

Measure the effects of bath parameters and other treatments upon the intermetallic compound layer and the root cause of brittle fractures in SAC Alloys-Microvoids
Support Electronic Industry efforts to improve the Reliability of SAC Alloys
Obtain quantitative results that will provide corrective action guidance to industry to mitigate the occurrence of brittle failures in drop or shock; for example cell phones
Develop fracture mechanics models that account for the effect of microvoids and intermetallic compounds material properties in simulated loads
Evaluation of the Solderability of an Alternate Alloy

This project is a part of General Purpose Lead Free assembly system, which has been planned to define a guideline compatible with tin-lead based soldering. Although tin-silver-copper solder pastes are in mainstream of lead-free, the composition of the pastes differs in areas. Europeans and North Americans would like to use Sn- (3.8-4.0) Ag- (0.6-0.7) Cu, whereas Japanese would like to use Sn-3.0Ag-0.5Cu. As HDP User Group had not had any experimental data about the Sn-3.0Ag-0.5Cu paste, the Japanese team decided to evaluate the solderability of this composition as an Alternate Solder Alloy. We hope that HDP User Group will be able to gather tremendous data and findings by sharing this activity with European / American activities on the Sn- (3.84.0) Ag- (0.6-0.7) Cu.

Lead Free Board Materials Reliability Phase 2

This is a follow up to the Lead Free Board Materials Reliability Project. New materials and formulations are tested to see how much improvement has been accomplished since the first project.

SAC Aging Factors - A

Endeavor to answer the following questions: What is the effect of aging time (post assembly) on SAC solder joint reliability? What is the effect of aging temperature?  How does SAC305 compare to SAC387?  How does strain level interact with aging?

Predict Lead Free Solder Joint Life from Microstructure Evolution

The aim of this project was to predict the remaining life of LF solder joints by analyzing the joint's microstructure after the board has been in service for several years where some fatigue damage has occured but the joint has not yet cracked.Test vehicles, as well as field returns, were micro sectioned and analyzed for structural change.  Observed structural changes were correlated to failure and field life. 

Lead Free Board Materials Reliability 3

This project is the third phase of an initiative originally started in 2006 to assess the performance of latest generation (at the time) PWB laminate systems after being exposed to simulated Pb-Free surface mount soldering conditions.  The third phase looked at recently released materials and focused on laminates designed for high speed applications. The project submited selected laminate systems to an extensive mechanical and electrical integrity testing program to verify whether the materials are prone to deterioration during higher temperature soldering conditions. 

GPLF Optimization Study

The introduction of RoHS and similar environmental legislation has driven the need to transition PCB products to be manufactured with Pb Free solder. While simpler designs can be produced with alternative Tin Solder Copper solder with little difficult, manufacturing larger and more complicated products, with high reliability demands, presents significant challenges, specifically in minimizing thermal stresses on certain components through the SMT solder reflow process. In order to overcomethese issues, process optimization is essential.

Mild Acceleration Factors
  • Current testing (industry and consortium) of Pb-free assemblies in accelerated conditions (0-100C, -40 to +125C, etc.) shows significant reductions in solder joint reliability (SAC reliability <<SnPb) for certain component types (high strain components).  These components are used on the majority of high reliability products.  There are no accepted acceleration factors or models for SAC reliability that relate accelerated conditions to field conditions.
  • The data available also indicates that SAC reliability SnPb for low strain components.
  • Aging factors affecting microstructure, creep and fatigue on SAC alloys have only recently been identified.
SAC Aging 2

There is evidence that the ATC performance of SAC solders is affected by thermal preconditioning or aging.  This project will use an existing test board design and component(s) to facilitate the further understanding of this phenomenon, and attempt to relate ATC performance to microstructural changes that occur during aging.  Baseline microstructural characterization will be performed on ambient (no age) and aged samples. Failure mode analysis and characterization will be performed on ATC samples to determine extent of microstructural evolution and impact on final failure.

Project type: Opto-Electronics

Address performance limitations encountered in high-speed electrical backplanes (15-20+ Gbps) by use of optical signal transmission.  Demonstrate, by building a test vehicle design, that optical waveguides within a backplane can benefit the system’s interconnect topology by providing: Higher data rates, Additional I/O, and better interconnect architectures

Optical FPC Assembly

This project evaluates the various manufacturing options for attaching very fine pitch flexible printed circuits typically used to connect optical transceiver modules to PWBs. The project will explore several different attachment techniques assessing their suitability for high volume high yielding assembly applications.

Project type: Power Supply
Board Mount Power Supply (BMPS) Guideline II

System integrators want to have well defined lead-free requirements on Board Mount Power Supplies (BMPS), Pin compatibility between functionally compliant BMPS, and industry standards for function compatibility of BMPS.  They also want to eliminate the need for modules to be attached using "press fit technology" or manual soldering.  Update and extend the information available in the BMPS Guideline.  Issue an updated version of the Guideline.

Board Mounted Power Supply evaluation

Power bricks are one of few “hold-out” components still demanding wave solder. The conversion to SMT bricks would allow the elimination of wave processing for many printed circuit assemblies. Currently 1/16th and 1/8th brick types have wide adoption in SMT with a variety pin/leg styles, this is not the case for the 1/4 brick and above sizes.

 This project focuses on the impact of DC/DC module (bricks) features on soldered PTH hole-fill and the module-PWB attachment reliability of SMT bricks. The project will measure the impact of various brick pin and footprint feature variants such as, gas vents, hole size, and thermal plane connections on the hole-fill of a pin through hole soldered joint. Besides the PTH configuration, SMT attach variants to be studied are “Pure Post”, “PIP/SMT hybrid”, and “Pedestal and ball”. Figure 18 shows a Pedestal and Ball configuration. Different brick styles will be studied in a 1/4 brick package to assess comparative thermal cycling and vibration reliability with the bricks carrying full current.

Board Mounted Power Supplies (BMPS) Guideline I
The cooperation shall consist of the following items:

PSMA and EPSMA would support the “General Purpose Lead-free Assembly System” concept. It is understood that several details of the assembly system remains to be defined

Project type: Printed Wiring Board Technology
PTH Lifetime Predictor for TC

Leveraging on results obtained from earlier Thin Cu Plating project, this project aimed to establish a popular equation to predict PTH lifetime, focusing on PWB used in the telecommunication equipment, computers and servers. Using finite element method (FEM) and applying Box-Behnken experimental design, seven PWB factors were initially analysed, by simulating pressures acting on several PWB models, under various operating environments. The relationships of these factors were established to derive the PTH lifetime predictor for TC (Temperature Cycling). Thermal cycling tests (TCT) were performed to compare the physical time to failure with the simulated one. 

Electro-Chemical Migration

The current industry standard test protocols were originally developed to identify highly ionic contaminant levels (halides) after a cleaning process.  Various forms of corrosion and ECM damage resulting in field failures on products that passed the current cleanliness and corrosion resistance test protocols has demonstrated that these test procedures are not completely effective. The current industry excepted testing does not take into consideration various acceleration factors associated with no clean flux and product design features.

This project was designed to create and evaluate the failure mechanisms, identify the gaps in the existing test methods, and identify modifications to the test methods required to predict where a failure will likely occur. The project collected and evaluated test data and drafted proposed changes to existing test methods, test protocols and the IPC and JEDEC specs.



PWB Back Drilling Failure Analysis

Back drilling or controlled depth drilling of plated through holes (PTH) is increasingly being used in High Speed Designs. While back drilling of PWB's helps to remove signal distortion by removing via related stubs, reliability issues attributed to this practice appear to be on the rise. The drivers for this project include the lack of Design Guidelines, PWB Fabrication Tolerances, Material and Lead Free Assembly. This project also evaluated new electrical methodologies for measuring copper stub length and depth of the backdrill along with determining exactly where the layer of interest (no cut) lies in the PCB board stack up.

Focus/Area of Concern: This project explored the reason for back drilling related PWB failures and to identified potential solutions and design/process guidelines to prevent future problems associated with this process.

·         The project assessed the backdrill capability of the Industry through a survey. The Survey targeted both OEM and PCB fabricators. The results were coded to keep all data anonymous.

·         Evaluated the reliability of backdrilled via compared to standard plated through hole. Designed a set of IST coupon that were tested as received, pre-conditioned (6X @ 260 C) and after simulated reflow.

·         Developed and analyzed a series of electrically testable backdrill coupons for stub length and inner layer laminate thickness measurement

Digital Speckle Correlation (DSC)

The Digital Image Speckle Correlation Project (DISC) is an experimental physics-based study, which will assess whether a unique but mature Digital Image/Speckle Correlation test method for the measurement of the thermal stress in microvias and surrounding areas can be used to predict the relative reliability differences in PWB stackup structures. The unique quantitative measurement of the strain and other deformation kinematic parameters makes it possible for a relatively short term mechanistic-based failure analysis instead of having to perform long term traditional reliability studies.

PWB Back Drilling Phase 2

Phase 1 of the project showed that the shallow back-drill fails earlier relative to the medium and deep back-drill and proved the capability to electrically measure remaining stub lengths from a single ended trace on a single inner layer position.  Phase 2 will focus on the shallow back-drill but on a much thicker 30 layer PCB using two heating circuits and will evaluate the capability to electrically measure via stubs from various layers within the 30 layer PCB TV using differential signal traces.

Ultra-Thin HDI Multi-Purpose Test Vehicle

As the electronics market is driven more and more by smartphones and notebooks, the rigid boards become smaller and thinner which only amplifies the lag between the current process methods/test vehicles and the design capabilities. This gap presently is as much as a decade behind.  As the gap grows, the older test vehicles become obsolete and are no longer applicable.  Each new product requires a unique test vehicle and modified process methods.  This engineering effort drives delays in production and manifests itself in increase costs for both OEM and suppliers.
The process methods used along with the current test vehicles used, do not capture interconnect density or thinness, they miss potential failure mechanisms (e.g., ion migration). In addition, the low density patterns introduce artifacts not seen in production before (e.g., distortion of via stack).  The test parameters may exceed practical limits of design or are inappropriate to application (e.g., 50V CAF).

As a result there is an increasing abandonment by the OEMs in favor of non-standardized “end product” test vehicles.  This only widens the gap between up-stream development & down-stream practice.  The only resolution is that the problem must be solved by the component, PCB & material supply-chain companies, because the OEMs are working in a black box.


Pad Cratering

Lead-free (LF) solder joints are stiffer than tin-lead solder joints, and LF compatible (Phenolic-cured) PCB dielectric materials are more brittle than the FR4 (dicy-cured) equivalent. These two factors, coupled with the higher peak reflow temperatures used for lead-free assemblies, could transfer more strain to the PCB dielectric structure, causing a cohesive failure underneath BGA corner pads. This project will examine the phenomenon with the goal of determining test and screening methods.

Thin Cu Stress Test

The reliability of plated through hole copper (Cu) in Printed Wiring Boards (PWB) is typically evaluated using air-to-air thermal cycling.  This takes a long time, and does not provide material data that can be used for finite element modeling of the structure.  This project will evaluate the use of rapid cycle stress testing to evaluate thin Cu and provide good material properties.

Multiple Lamination

As BGA pitch decreases and I/O count increases, stacked microvia designs become more prevalent However, there is little data in the public domain on the reliability of these stacked designs. Previous studies done by PWB Interconnect Solutions and EIT showed that there can be a significant reliability degradation of stacked microvias in certain constructions. This project is designed to evaluate 2, 3, and 4 stack microvias both “stand alone” and stacked on buried via  and compare the data to a plated through holes (PTH) using Interconnect Stress Testing (IST) and TMA/DMA/TGA testing.  The test vehicle will consist of three different thicknesses (.062, .093, and .125) with two different laminate materials and will simulate 0.8/0.4mm and 1.0/0.5mm BGA pitches. The extended process time at high temperatures in multiple lamination designs coupled with multiple assembly cycles and rework cycles may cause stress that are undocumented. Participants in this project will receive statistically accurate data on stacked HDI reliability.

Smooth Copper Signal Integrity

The High Density Packaging (HDP) user group has completed a project evaluating the high frequency loss impacts of a variety of imaged core surface treatments (bond enhancement treatments, including chemical bonding and newer low etch alternative oxides) applied just prior to press lamination. Initial high frequency Dk/Df loss measurement results did not show a strong correlation with any of the methods utilized within this project to measured surface roughness. The more significant factor affecting the measured loss is the choice of pre-lamination surface treatment.  Most of the new chemical treatment systems outperform the older existing systems which depend upon surface roughness techniques to promote adhesion.

PWB Environmental Life Cycle Analysis

An environmental life cycle analysis study measures the CO2 emissions and energy consumption associated with the full life of a product including the impact from raw material extraction, manufacturing processes, transportation/packaging, operational life and end of life disposal. The technique is becoming increasingly recognized as an important measure for determining the impact of electrical products. This project focused on the environmental consequences of producing and using printed wiring boards and  involved representatives from the complete PWB supply chain.


Counterfeit PCB Materials

The Counterfeit PCB Materials Project identifies and investigates two issues in the electronics industry: Safety as a function of counterfeit materials, and Trust   involving anti-counterfeit, anti-tamper, chain of custody and access control.

PWB Environmental Life Cycle Analysis 2

Building on the results from phase 1 of the project the Phase 2 will develop a more flexible PWB fabrication Green House Gas (GHG) emissions calculator. It will have added capability to support advanced/emerging PWB materials. Phase 2 will also raise greater industry awareness of the project and engage with other organizations / companies. We will also increase industry awareness by external publication.

Project type: Emerging Technology
TSV Board Level Reliability

Through silicon vias (TSV) offer a potential solution to addressing some of the interconnect issues that impact the CPU-Memory latency bottle neck. This project focuses on how TSVs can be adopted for this purpose and evaluates the challenges to applying this technology in future packaging solutions.  Possible exploration areas might include reliability of TSV interconnect, road mapping, fabrication of high density TSV, and/or design tools.

Anti-Counterfeit Electronics

The project will define the optimum Protocols for forward and backward traceability that provide built-in integrity to transactions throughout the electronics supply chain, evaluate the technologies that support those protocols and conduct a multi-link test to confirm applicability and effectiveness of the selected protocols and technologies.

Anti Counterfeit of Electronics Phase 3

The High Density Packaging User Group announces Phase 3 of the Anti-counterfeit of Electronics Project. Building on Phase 1 of this project in which the team defined the protocol for information required to pass down (and up) the Supply Chain for traceability. In Phase 2, the team identified current and emerging technologies capable of transmitting the required information along the Supply Chain and mapped the technologies against the segments of the Supply that they may be best suited for. Phase 3 allows the team to test selected technologies to confirm applicability and effectiveness of those protocols and technologies.

Anti Counterfeit Phase 2

Phase 2: List, evaluate and compare the existing and emerging technologies for product authentication throughout the electronics supply chain that support the protocol, their applicability and effectiveness at all stages.

TSV Signal Integrity

TSV (Through-Silicon Vias) Signal Integrity Project:  (Lead: NIST)
This project was initiated as an evaluation of the status of TSV, and during that evaluation, identified some potential avenues of exploration for HDP User Group. The Signal Integrity project was first proposed in February 2014, entered the Definition Phase in June 2014, and was concluded in April 2016.  The approach here was to generate an experimental project to compare the signal quality of TSV packaging to traditional packaging. 
This empirical approach required the procurement of hardware which to-date has not been made available for non-proprietary experimentation. 
Benefits of the Project:
To conclude this project, Yaw Obeng and Dave Love wrote up a short review, summarizing of the current status of the public knowledge of TSV signal integrity. This summary can be found on the website in the Projects section. In that document, there are 14 references to published work on the topic.
Project type: Lead Finish
Lead Free Assembly Guideline - Version 3.0

The General Purpose Lead Free (GPLF) assembly system guideline was originally developed in 2004 with a minor revision added in 2005. The aim of the document was to produce a handbook that would assist system integrators/ electronics producers and their supply chain in developing Pb-Free manufacturing solutions that meet required levels of reliability while complying with forthcoming environmental legislation.

The guideline has not been revised since 2005 and is in urgent need of updating. The proposed Guideline – 3rd Edition Project is therefore aimed at making the document more relevant to the current challenges and issues faced by the industry.

Component Terminal Finishes Phase 3

This project measures MSL results by surface treatment type and development results of new NiPd-based finishes for enhanced MSL, based on the results presented in Phases I and II.  Data includes the use of surface treatments and finishes such as Cu surface Zn-Cr coating (A2 coating), Micro Etching, Brown Oxidation Treatment and Surface Adhesion Promoter Coating.

Component Terminal Finishes Phase 2

Various techniques have been proposed to reduce the Sn-whisker risk with matte Sn finishes. Nevertheless, most end users of electronic still have concerns about long term Sn-whisker growth risk with Sn based terminal finishes. NiPd-based Pre-Plated lead Leadframe (PPF) finishes have been introduced as one Pb-free alternative with no Sn-whisker risk. An improved technology that overcomes the technical limitations of the existing NiPd-based finishes has been developed and applied extensively, but degradation in the Moisture Sensitivity Level (MSL) of a package component due to the limited adhesion quality between compound and noble metal surface and the increase in Pb-free SMT temperature (260℃) has occurred more frequently with NiPd-based finish packages.

Nickel-Palladium Based Component Terminal Finishes I

Erroneous perceptions such as high cost driven by Pd content and price, quality problems at board mounting, and package reliability limits MSL(Moisture Sensitivity Level) have led some IC component suppliers to reject adopting or even evaluating NiPd based PPFs.

Project type: Printed Wiring Board Assembly
Mechanical Fatigue Test for Solder Joint Reliability - A
Shortening of the product development cycle requires a new method that can evaluate the reliability of solder joint in the short time instead of the conventional thermal cycle test.
There are several proposals on the solder joint reliability test using the mechanical fatigue test from universities and an institute. Mechanical shear fatigue test have been proposed to IEC standards.
Low/No Silver Alloy Solder Paste Phase 1 Process Characterization


The price of metals and particularly silver (Ag) has been increasing in recent years. This has created an increased interest in the use of low/no silver alloy in the manufacturing process. Low silver alloy BGA solder balls (such as SAC105) are being used in products, but there is very little information about the alternative (low/no) silver alloy solder pastes, it’s process feasibility and reliability. Within the past couple of years, many alternative low/no silver alloy solder pastes have been developed and are available in the market.

 This is a multi-phased project, the first phase was designed to characterize the candidate solderpaste to verify that they could be used to assemble the Phase 2 reliability components. Phase 2 will evaluate the reliability of some of the candidate solderpaste.

 The Phase 1 project studied and documented the process feasibility/characterization of low/no silver alloy solder pastes compared to the standard SAC 305 paste for integration into a development assembly line.

 Phase 1 studied the process feasibility and reliability of low/no silver alloy solder pastes including

 ·         Low/no silver high temperature alloy solder pastes (liquidus temperature >217°C)

 ·         Low/no silver low temperature alloy solder pastes. (liquidus temperature <217°C)


Mechanical Fatigue Phase II - A

This is a follow on to the Phase I Project which showed some promise for using rapid mechanical stressing to predict quality and life of Lead Free solders, but much quicker than conventional thermal cycle.  This project will study the difference of fatigue life in solder joints of leadless packages (QFN packages) between conventional temperature cycle test and mechanical fatigue test.  It will also study the similarities and differences at the same maximum strain in solder joints between mechanical fatigue and bending test.

Press-Fit Technology Rework

More and more products use electronic devices to communicate, in 2020 it is expected that there will be more than 50 billion connected devices in the world. This means that many electronic products, especially mobile base stations and core network nodes, need to handle enormous amount of data per second. One important link in this communication chain are high speed press fit connectors that are often used to connect mother boards and back planes in core network nodes. These new high speed press fit connectors have several hundred thin, short and frail pins that easily could be damaged if not produced and handled correctly. Figure 35 shows a high speed press fit connector. These new connectors are very expensive and small variations in via hole dimensions and hole plating thickness will affect the connections for these sensitive press fit pins. If the holes are too small, the pins will bend.  If the holes are too big, they will not form a gas tight connection.

Project type: Component Packaging
FCBGA Package Warpage
Most of the assembly industry is experiencing problems with the ever decreasing IC package thickness.  With denser packages (QFN's, Area Array's and Stacked Packages), the flatness of the packages and boards becomes more and more critical.
Warpage as a result of the thickness of the IC's used, can be a manufacturing night mare.  Defects such as open joints or very weak joints can be caused by short leads on the IC's combined with very flexible carriers.  This combination will most likely cause interconnections that will be poorly made or never made, resulting in a defect.
With the IC's becoming increasingly thinner, the silicon has less impact on resisting deformation of the package. The net result is that warpage will become an increasing problem in the future.

Advanced QFN Evaluation

This project explored component footprint design and associated circuit board assembly processes for the latest generation of fine pitch QFN devices. The project conducted both post assembly yield assessments and longer term reliability testing (using accelerated thermal cycling techniques) to evaluate the impact of using different design and process parameters.

FCBGA Package Warpage 2

Warpage is an assembly manufacturing problem resulting in opens, weak joints, Head on Pillow (HOP) and None Wet Open (NWO) defects. With the IC's becoming increasingly thinner, the silicon has less ability to resist deformation of the component package. This deformation combined with short IC leads and a very flexible substrate often exceeds the termination-to-solder paste gap.  The net result is that warpage will become an increasing problem in the future.  Warpage as a result of the thickness of the IC's used,along with defects such as open joints or very weak joints can be caused by short leads on the IC's combined with very flexible carriers. This combination will most likely cause interconnections that will be poorly made or never made  In phase 2 of this project, we will characterize the newly defined process from FCBGA Package Warpage 1 and develop a consistent methodology to use in normal production.

Polymer Ball Interconnect - A

The use of plated polymer cored balls to replace solder balls in BGAs and CSPs has been developed and trailled  over several years but has yet to see signifcant take up in the industry.  However with larger ceramic components presenting increasingly challenging long term reliability concerns the flexible nature of polymer ball technology is becoming increasingly attractive.This project looked into latest products from  two polymer ball manufacturers, including multiple polymer compositions, coatings and soldering methods. Bend testing and thermal cycling were conducted on different size ceramic BGAs.  The project team was made up of member companies from across the supply the supply chain.

Thermo-Electromigration in WL-CSP Pb-Free Solder Joints
TE-Migration II
Wafer Level Packaging Materials

A coordinated activity within the Materials/Wafer Fabricators/OEMs supply chain to quickly and thoroughly evaluate new material options.  Increasing pace of new materials introduction by multiple suppliers can overwhelm design, packaging, and testing resources –if everything is evaluated.  By the time a material (i.e., mold compound, repassivation, coating, doped solder, etc.) is qualified, newer “improved’ materials are offered.  An effort like this is needed to quickly determine the best alternatives, and significantly reduce the cost and effort by the suppliers, by focusing on the specific needs of the OEMs and ODMs.  When we are finished, the users will be ready to implement the alternatives, because they have been part of the development.

Process Sensitive Components

This project is intended to compile and publish an industry guideline document on recommended practices for the treatment of temperature sensitive components (TSC). This guideline will include inputs from IC component, non-IC component, and connector suppliers as well as OEM users and Contract Manufacturers. This document will also identify Best Practices for assembling process sensitive components, along with other component process sensitities.

Project type: High Frequency
High Frequency Measurements Phase 3

Particiapnts in this project will  evaluate the effect of moisture on each of the high frequency Dk and Df test methods. During the testing and analysis of the earlier phases of this project, it was determined that there were strong Dk and Df data correlations between high frequency test methods that were of the same type (Z-direction, Trace, and In-plane). However, differences in moisture content were found to contribute up to a 20 percent difference in the measured Df values of some laminate materials tested.


High Frequency Loss from Copper Topology

The recently completed Smooth Cu Si project suggested a difference in the X versus Y axis topography of the drum side of the copper foil after some treatments could affect insertion loss. This project will delve into the question of how this copper directionality or topography can affect insertion loss and evaluate the level of this loss.

X-Ray Tomography Signal Integrity

Dr. Sven Simon and his group at the University of Stuttgart developed a new method of inputting high definition three dimensional (3D) X-ray images into 3D Electromagnetic Field Solvers.  Dr Simon provided the equipment and carried out the experimental work. This method is based on software developed at the University of Stuttgart.  Figure XX shows an actual image of the inside cabinet of the x-ray equipment.  After several system upgrades, the basic technique was demonstrated, the accuracy and precision of the dimensional measurements were confirmed and experimental work was carried out to verify the best vector network analyzer probes to use. This project is a useful adjunct to the award-winning High-Frequency Materials Project. Coupons from the HF Materials project were sent to U. Stuttgart after completing Df/Dk testing.  With the detailed preliminary work completed, X-ray and VNA measurements were collected for the supplied coupons and the necessary data uploaded into the solver.  Comparison of the results obtained by more traditional methods were carried out.

High Frequency Flex