Projects

Current projects

Classic CAF (Conductive Anodic Filamentation) is a two-step process, firstly the creation of a pathway by hydrolysis followed by electrochemical filament growth. Where there is no pathway there can be no CAF, hence existing acceleration factor equations which model the process as a single step are clearly incorrect. The project will determine a better acceleration factor equation for CAF and quantify the effects of voltage, temperature and humidity hopefully enabling shorter testing time for CAF material qualification.

Project type: Printed Wiring Board Technology Project stage: Definition

The purpose of this project is to determine the effect of varying board thickness on the solder joint reliability (SJR) of a variety of devices that are attached to those boards. Opinions, modeling results, and data on this topic are conflicting. There have been no definitive studies published.

Project type: Printed Wiring Board Technology Project stage: Implementation

CAF (Conductive Anodic Filamentation) is normally characterized as an effect subject to the influences of design, process and materials. This adds complication to product development for laminate manufactures as lengthy failure analysis is normally required when CAF testing is performed using standard test vehicles. The project aim is to develop a test vehicle that will allow performance evaluation to be limited to laminate material only, thus eliminating the variables of design and process. It is expected that the project will lead to more focused and quicker laminate testing and development for CAF resistance.

Project type: Printed Wiring Board Technology Project stage: Definition

Current rework guidelines regarding the number of allowable reworks for a component site are inadequate and need to be upgraded or better understood with solid research.  This project proposes to establish a limit for the number of reworks that can occur for components or particular component types on an assembly without impacting the overall reliability. The project will develop new guidelines for reworks to be used in PWA and will write a proposal for new specifications on rework of PWA which will be delivered to standards bodies for their consideration.

Project type: Printed Wiring Board Assembly Project stage: Implementation

Previous results from the Pb-Free PWB materials reliability project have indicated that for the MRT test board used there is a clear relationship between design features and the increased risk of material delamination through SMT reflow. Using modified design variants of the MRT test board, this project explores further the impact of reduced through hole via pitch and hole wall to hole wall spacing, board thickness, number of layers and position of power distribution planes on the occurrence of post SMT assembly material damage.

Project type: Printed Wiring Board Technology Project stage: Implementation

This project is a continuation of the Digital Speckle Correlation (DSC) Project, which consisted of a preliminary look at the reliability for on and off-stack buried structures by measuring the strains the structure see going through a reflow process.  The name of the new project has been changed to Digital Image Speckle Correlation 2 (DISC2) for two reasons.  Obviously, it is a continuation of the previous project and the other reason is to not use the DSC acronym, which is more commonly used for Differential Scanning Calorimetry, a technique which has nothing to do with the previous or the new, current project.  The recently completed DSC Project used coupons from the very successful completed Multi-lam Project.  For the DISC2 Project the Team will expand the scope of investigated structures.  

This project will create empirical data which could be used in modelling tools, such as DFR’s Sherlock, CALCE’s SARA or full blown FEM tools such as ANSYS.  The resultant model could predict reliability and give an evaluation of design trade-offs.  The Digital Image Speckle method is much quicker than Accelerated Thermal Cycling, which can take months.

Project type: Printed Wiring Board Technology Project stage: Idea

In our previous project Electro-Chemical Migration we found that a No Clean Flux, which is designed to leave a benign residue, can result in crevice and pitting corrosion. We also discovered the flux activators can remain on the board due to excessive flux or entrapment (ie,: Selective solder fixtures, Wicking into soldermask and Non solder mask defined pads).  We already knew that harsh environments subjects devices to high humidity.  This all means that Ions can be mobilized and cause corrosion on exposed copper features.  In this follow-on project we would like to develop a Test Method for determining Pitting / Crevice Corrosion capability of a Solder Flux. We then would submit the method to IPC Cleaning and Coating Committee for consideration of an additional test within J-STD 004 to evaluate flux potential to propagate Pitting / Crevice Corrosion capability of a Solder Flux on Cu and Sn and subsequently work with the IPC Committee on Cleanings and Coatings to implement our recommendations.

Project type: Printed Wiring Board Technology Project stage: Definition

Warpage is an assembly manufacturing problem resulting in opens, weak joints, Head on Pillow (HOP) and None Wet Open (NWO) defects. With the IC's becoming increasingly thinner, the silicon has less ability to resist deformation of the component package. This deformation combined with short IC leads and a very flexible substrate often exceeds the termination-to-solder paste gap.  The net result is that warpage will become an increasing problem in the future.  Warpage as a result of the thickness of the IC's used,along with defects such as open joints or very weak joints can be caused by short leads on the IC's combined with very flexible carriers. This combination will most likely cause interconnections that will be poorly made or never made  In phase 2 of this project, we will characterize the newly defined process from FCBGA Package Warpage 1 and develop a consistent methodology to use in normal production.

Project type: Component Packaging Project stage: Implementation

BGA pitch is moving steadily downward and high I/O BGAs are common at 1.0mm and 0.8mm pitch and starting to appear at 0.65mm pitch. Consumer PCB’s (smart phone, tablet, etc.) have already moved to large I/O BGA’s at 0.5mm and even 0.4mm pitch. This technology density is often supported by “Any Layer/Every Layer HDI PCB’s”. Generally the PCB’s used in Any Layer designs are very thin (typically 0.8mm thick or less). High density packages require 3 + stacks of microvias for routing (depending on how many I/O and design specifics) just to escape route these packages. It is inevitable that high I/O BGAs for high complexity products (Telecom, Server, etc.) will also trend downward in pitch, following the consumer trend.

 

Project type: Emerging Technology Project stage: Implementation

Materials used in Electronic Products are getting more and more scrutiny by government agencies around the globe (RoHS, REACH, CA Prop 65 etc). To date the U.S. Military has not shown a strong interest in halogen free laminate. However some military analysts feel there is a need to understand if halogen free laminates can withstand the more rigorous military testing criteria. This project will evaluate several laminates using military / aerospace reliability testing criteria.

Project type: Printed Wiring Board Technology Project stage: Idea

This project proposes to evaluate lead free solders that may be suitable for harsher environmental and use conditions such as transportation, and defense applications.

Project type: Lead-Free Project stage: Implementation

This project characterized the effect on signal integrity for flexible printed circuit boards operating at high end digital transmission frequencies as a function of different cross hatched ground plane design features and materials.  Cross hatching (non-contiguous planes) vs. solid planes were evaluated in order to understand how the cross hatch designs effect impedance and S parameters (insertion and return loss).  Test vehicles were built with the various features (line widths, line spacing, and total copper in plane).  These were used to measure the S parameters/impedance up to 20 GHz, and the data collected was compared to present day models (2D and 3D simulations).

Flexible printed circuits (FPCs) provide a practical option for interconnection of printed circuit boards and electronic modules, particularly where space is constrained or weight is a factor. Moreover FPC construction offers greater levels of impedance control compared with co-axial and other wired connections. However with FPCs increasingly being used in high speed digital applications, understanding their electrical performance at high frequencies becomes a growing challenge. This project is characterizing the effect on signal integrity for flexible printed circuit boards operating at high end digital transmission frequencies (up to 20 GHz) with regards to different design features, specifically cross hatched ground planes.

 

Project type: High Frequency Project stage: Implementation

The recently completed Smooth Cu Si project suggested a difference in the X versus Y axis topography of the drum side of the copper foil after some treatments could affect insertion loss. This project will delve into the question of how this copper directionality or topography can affect insertion loss and evaluate the level of this loss.

Project type: High Frequency Project stage: Implementation

Phase 5 of the Lead-Free PWB materials reliability program will evaluate selected latest generation PWB laminates. The testing program will include thermal analysis and stress testing, thermal cycling endurance, susceptibility to CAF and evaluation of electrical characteristics at high frequencies using a new connectorless SPP (short pulse propagation) design. Properties will be evaluated both before and after multiple simulated reflow conditions.

 

Project type: Lead-Free Project stage: Implementation

The Low Ag/No Process Characterization study of low Ag alloy solder paste showed that the candidate materials tested can be used in the process without major assembly defects. This project will evaluate the reliability of a selection of these solderpastes in comparison to the standard SAC305 paste for integration into a development assembly line. This is a two phase project, Phase 1 will assemble and test a QFN component to down select alloys for the following BGA Phase 2 which plans to assemble and test a BGA component with a SAC305 solder ball and the various candidate solderpaste.

 

 

Project type: Printed Wiring Board Assembly Project stage: Implementation
Network capabilities must now accommodate increasing demands for data transmission from business and consumer customer bases over fixed access and wireless networks at any time of day or night. These high traffic operational modes, coupled with energy saving modes at the component level, have the potential to induce new reliability challenges by adding new types of thermomechanical stress and strain to equipment. Rapid and frequent mini-power cycling is now being coupled with the well-known stress from diurnal cycling and typical thermal operating conditions. Network operations have long avoided traditional power cycling because power cycles are known to degrade solder joint performance and reduce the life and performance of hardware. The advent of Sn-based, Pb-free alloys for solder assembly is expected to increase susceptibility to power cycling-induced damage.
 
Project type: Lead-Free Project stage: Implementation

Phase 2 of the HDP optoelectronic is a demonstrator.  The project is designed to show the trends in bandwidth and speed may be implemented in an electro/optical environment. Several different waveguide technologies are evaluated in the project, using a prototype system level demonstration vehicle. The demonstrator has physical attributes found in today’s systems such as: routers, switches, and storage systems. Its’ design relies on photonic components to solve many limitations of electrical interfaces.

The channels are a mix of polymer waveguides and fibers to enable high bandwidth per link at speeds exceeding 40  Gb/s per channel. The pseudo system is composed of  line cards that will be inserted into a  “slot chassis” type of architecture to mimic today’s systems. These line cards are interconnected using optical links and transmit and receive high bandwidth and high speed signals through an optical backplane.

Project type: Opto-Electronics Project stage: Implementation