The purpose of this project is to determine the effect of varying board thickness on the solder joint reliability (SJR) of a variety of devices that are attached to those boards. Opinions, modeling results, and data on this topic are conflicting. There have been no definitive studies published.
Current rework guidelines regarding the number of allowable reworks for a component site are inadequate and need to be upgraded or better understood with solid research. This project proposes to establish a limit for the number of reworks that can occur for components or particular component types on an assembly without impacting the overall reliability. The project will develop new guidelines for reworks to be used in PWA and will write a proposal for new specifications on rework of PWA which will be delivered to standards bodies for their consideration.
Previous results from the Pb-Free PWB materials reliability project have indicated that for the MRT test board used there is a clear relationship between design features and the increased risk of material delamination through SMT reflow. Using modified design variants of the MRT test board, this project explores further the impact of reduced through hole via pitch and hole wall to hole wall spacing, board thickness, number of layers and position of power distribution planes on the occurrence of post SMT assembly material damage.
In our previous project Electro-Chemical Migration we found that a No Clean Flux, which is designed to leave a benign residue, can result in crevice and pitting corrosion. We also discovered the flux activators can remain on the board due to excessive flux or entrapment (ie,: Selective solder fixtures, Wicking into soldermask and Non solder mask defined pads). We already knew that harsh environments subjects devices to high humidity. This all means that Ions can be mobilized and cause corrosion on exposed copper features. In this follow-on project we would like to develop a Test Method for determining Pitting / Crevice Corrosion capability of a Solder Flux. We then would submit the method to IPC Cleaning and Coating Committee for consideration of an additional test within J-STD 004 to evaluate flux potential to propagate Pitting / Crevice Corrosion capability of a Solder Flux on Cu and Sn and subsequently work with the IPC Committee on Cleanings and Coatings to implement our recommendations.
Warpage is an assembly manufacturing problem resulting in opens, weak joints, Head on Pillow (HOP) and None Wet Open (NWO) defects. With the IC's becoming increasingly thinner, the silicon has less ability to resist deformation of the component package. This deformation combined with short IC leads and a very flexible substrate often exceeds the termination-to-solder paste gap. The net result is that warpage will become an increasing problem in the future. Warpage as a result of the thickness of the IC's used,along with defects such as open joints or very weak joints can be caused by short leads on the IC's combined with very flexible carriers. This combination will most likely cause interconnections that will be poorly made or never made In phase 2 of this project, we will characterize the newly defined process from FCBGA Package Warpage 1 and develop a consistent methodology to use in normal production.
BGA pitch is moving steadily downward and high I/O BGAs are common at 1mm and 0.8mm pitch today and starting to appear at 0.65mm pitch. Consumer PCB’s (smart phone, tablet, etc.) have already moved to large I/O BGA’s at 0.5 and even 0.4mm pitch. This technology density is often supported by “Any Layer/Every Layer HDI PCB’s”. Generally the PCB’s used in Any Layer designs are very thin (typically 0.8mm thick or less). Participants in this project will determine the maximum PCB thickness that can be supported with “Any Layer” designs. The uniqueness of this project is the project is a new construction concept merging aspects of today’s high end telecom/computer designs with aspects of consumer PCB’s. There is no other similar project known to have been proposed or completed.
This project proposes to evaluate lead free solders that may be suitable for harsher environmental and use conditions such as transportation, and defense applications.
Flexible printed circuits (FPCs) provide a practical option for interconnection of printed circuit boards and electronic modules, particularly where space is constrained or weight is a factor. Moreover FPC construction offers greater levels of impedance control compared with co-axial and other wired connections. However with FPCs increasingly being used in high speed digital applications, understanding their electrical performance at high frequencies becomes a growing challenge. This project is characterizing the effect on signal integrity for flexible printed circuit boards operating at high end digital transmission frequencies (up to 20 GHz) with regards to different design features, specifically cross hatched ground planes.
Particiapnts in this project will evaluate the effect of moisture on each of the high frequency Dk and Df test methods. During the testing and analysis of the earlier phases of this project, it was determined that there were strong Dk and Df data correlations between high frequency test methods that were of the same type (Z-direction, Trace, and In-plane). However, differences in moisture content were found to contribute up to a 20 percent difference in the measured Df values of some laminate materials tested.
Phase 5 of the Lead-Free PWB materials reliability program will evaluate selected latest generation PWB laminates. The testing program will include thermal analysis and stress testing, thermal cycling endurance, susceptibility to CAF and evaluation of electrical characteristics at high frequencies using a new connectorless SPP (short pulse propagation) design. Properties will be evaluated both before and after multiple simulated reflow conditions.
Phase 1 process feasibility study of low Ag alloy solder paste showed that the candidate materials tested can be used in the process without major assembly defects. Phase 2 will evaluate the reliability of these solderpaste. Phase 2 Reliability is a 2 leg project. The first leg will assemble and test a QFN component to down select alloys for next BGA leg. Leg 2 will assemble and test a BGA component with a SAC305 solder ball and the various candidate solderpaste.
As BGA pitch decreases and I/O count increases, stacked microvia designs become more prevalent However, there is little data in the public domain on the reliability of these stacked designs. Previous studies done by PWB Interconnect Solutions and EIT showed that there can be a significant reliability degradation of stacked microvias in certain constructions. This project is designed to evaluate 2, 3, and 4 stack microvias both “stand alone” and stacked on buried via and compare the data to a plated through holes (PTH) using Interconnect Stress Testing (IST) and TMA/DMA/TGA testing. The test vehicle will consist of three different thicknesses (.062, .093, and .125) with two different laminate materials and will simulate 0.8/0.4mm and 1.0/0.5mm BGA pitches. The extended process time at high temperatures in multiple lamination designs coupled with multiple assembly cycles and rework cycles may cause stress that are undocumented. Participants in this project will receive statistically accurate data on stacked HDI reliability.
Phase 2 of the HDP optoelectronic will demonstrate how the trends in bandwidth and speed to design for next generation systems will be fulfilled through optical waveguide technology. Phase 2 will bring a practical perspective to optoelectronics by building a prototype system level demonstration vehicle . This pseudo system will have physical attributes found in today’s systems such as: routers, switches, and storage systems. Its’ design will rely on photonic components to solve many limitations of electrical interfaces. The channels will be a mix of polymer waveguides and fibers to enable high bandwidth per link at speeds exceeding 50 Gb/s per channel. The pseudo system will be composed of linecards that will be inserted into a “slot chassis” type of architecture to mimic today’s systems. These linecards will be interconnected using optical links and transmit and receive high bandwidth and high speed signals through an optical backplane.
Lead-free (LF) solder joints are stiffer than tin-lead solder joints, and LF compatible (Phenolic-cured) PCB dielectric materials are more brittle than the FR4 (dicy-cured) equivalent. These two factors, coupled with the higher peak reflow temperatures used for lead-free assemblies, could transfer more strain to the PCB dielectric structure, causing a cohesive failure underneath BGA corner pads. This project will examine the phenomenon with the goal of determining test and screening methods.
More and more products use electronic devices to communicate, in 2020 it is expected that there will be more than 50 billion connected devices in the world. This means that many electronic products, especially mobile base stations and core network nodes, need to handle enormous amount of data per second. One important link in this communication chain are high speed press fit connectors that are often used to connect mother boards and back planes in core network nodes. These new high speed press fit connectors have several hundred thin, short and frail pins that easily could be damaged if not produced and handled correctly. Figure 35 shows a high speed press fit connector. These new connectors are very expensive and small variations in via hole dimensions and hole plating thickness will affect the connections for these sensitive press fit pins. If the holes are too small, the pins will bend. If the holes are too big, they will not form a gas tight connection
This project aims to establish an accelerated equation to predict PTH lifetime. This equation can be used to give a more accurate prediction of the product warranty period based on the product’s operating environment. It can also be used to find PTH critical design factors to fine-tune the PTH design at the early PCB design stage, bringing improvement to product lifespan. This project will focus on PCB used in telecommunication equipment, computers and servers. FEM will be used to simulate different PTH specifications and operating environments to compute the time to failure of the PTH. Thermal cycle tests will be performed to compare the physical time to failure with the calculated one. This process will be repeated to achieve the optimum result and establish the accelerated equation to predict PTH lifetime for TC.
Phase 1 of the project showed that the shallow back-drill fails earlier relative to the medium and deep back-drill and proved the capability to electrically measure remaining stub lengths from a single ended trace on a single inner layer position. Phase 2 will focus on the shallow back-drill but on a much thicker 30 layer PCB using two heating circuits and will evaluate the capability to electrically measure via stubs from various layers within the 30 layer PCB TV using differential signal traces.
Phase 1 of the PWB Environmental Life Cycle Analysis project focussed on developing a calculator to estimate green house emissions associated with fabrication of printed wiring boards. Data for this phase of the project was collected from two fabrication plants, one specializing in conventional multi-layer circuit boards and the other specifically set up to manufacture high density interconnect (sequential build-up) designs. Phase 2 of the project aims to extend the calculator so that it is adaptable to other fabrication plants and can also be used for non-standard designs. In addtion the team are looking to partner with other organizations to consolidate on process data collection.