Multiple Lamination

As BGA pitch decreases and I/O count increases, stacked microvia designs become more prevalent However, there is little data in the public domain on the reliability of these stacked designs. Previous studies done by PWB Interconnect Solutions and EIT showed that there can be a significant reliability degradation of stacked microvias in certain constructions. This project is designed to evaluate 2, 3, and 4 stack microvias both “stand alone” and stacked on buried via  and compare the data to a plated through holes (PTH) using Interconnect Stress Testing (IST) and TMA/DMA/TGA testing.  The test vehicle will consist of three different thicknesses (.062, .093, and .125) with two different laminate materials and will simulate 0.8/0.4mm and 1.0/0.5mm BGA pitches. The extended process time at high temperatures in multiple lamination designs coupled with multiple assembly cycles and rework cycles may cause stress that are undocumented. Participants in this project will receive statistically accurate data on stacked HDI reliability.

Project stage: 
Lead company: 
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Idea Information


 Many industry professionals are worried about the impact of ROHS on long term PWB reliability. With peak temperature differentials of approximately 30 degrees C, laminate parameters like CTE, Tg, and Modulus of elasticity are of major concerns. The stress on vias due to differential expansion and PTH failure modes like foil cracks, post separation, barrel cracks and corner cracks are all worrisome.


The extended process time at high temperatures in multiple lamination designs coupled with multiple assembly cycles and rework cycles may cause stress that are undocumented. This project will attempt to provide statistically accurate data on multiple heat cycle stresses. 

The below schematic diagram is a representation of the two different via systems that this project will evaluate

Stacked vias                                                          Staggered vias


Definition Information

Goals / Benefits: 


  • The HDP User Group membership willreceive six new IST coupon designs useable on any additional projects along with a detailed report containing the full variables data. The report will include an evaluation of thickness vs. reliability and CTE vs. reliability of the various microvia configurations.

  • The HDP User Group OEM’s, PWB designers and ODMs will learn what design configurations, material types/characteristics provide the highest and lowest design reliability.

High level objectives: 

The focus of this project is to evaluate the reliability of stacked micro vias. The evaluation will include stand alone and stacked on buried vias. Additional factors are board thickness, material CTE and BGA pitch.



A controlled experiment testing multiple lead free laminate survivablity with a non-lead free control.

            Potential specifications are:

                        4 - lamination cycles

• 6X@288ºC – cross-sections

• 6X@260ºC Reflow – cross-sections


• Other testing? TBD 

–Evaluate at 1mm and 0.8mm pitch

• Buried Via Array

• Through Via Array

• Stacked Microvias (2) on Buried Via Array


Flow Chart

Key Participants: 
Elite Material Co. EMC
Hitachi Chemical
Isola Group
PWB Interconnect Solutions
Rogers Corporation
TTM Technologies