Mini Power Cycles

Network capabilities must now accommodate increasing demands for data transmission from business and consumer customer bases over fixed access and wireless networks at any time of day or night. These high traffic operational modes, coupled with energy saving modes at the component level, have the potential to induce new reliability challenges by adding new types of thermomechanical stress and strain to equipment. Rapid and frequent mini-power cycling is now being coupled with the well-known stress from diurnal cycling and typical thermal operating conditions. Network operations have long avoided traditional power cycling because power cycles are known to degrade solder joint performance and reduce the life and performance of hardware. The advent of Sn-based, Pb-free alloys for solder assembly is expected to increase susceptibility to power cycling-induced damage.
 
Project stage: 
Project type: 

If you are interested in participating in this project:

Members - Go to the "Subscribe Here" section to the right and select the "Subscribe to space" key.

Non Members - Go to the "Contact" section to the right and select the "Contact project facilitator" key. 

Idea Information

Background: 

New use paradigms for network infrastructure hardware are becoming more common place with the ubiquity of work and new energy saving use approaches. Many network operators are requiring features that minimize power use by adding intelligence to network equipment. This enables them to power down during low use time but provide nearly instant on when an increase in network traffic is required. These energy saving power modes can be applied at the component level and even to specific locations in an IC device.

 

 
Problem: 

 

No data exists on the reliability impact of mini-power cycles on large array packages used for microprocessors. The mini-power cycling causes localized heating and cooling on the device, and Pb Free alloys are more susceptible to damage caused by cycling. Understanding the impact of mini-power cycling on reliability of processor cards is the main goal of this work.

 

 

 

Definition Information

Goals / Benefits: 

 

·       Data will be provided that enables members to quantify the impact that various power saving operations have on their products.

 

·       The design of the project’s daisy chained heater package can also be used for evaluation of thermal interface materials in the future.

 

·       The project will develop a test protocol for mini power cycles that does not exist today, which can be used as a baseline for future work by member companies.

 

High level objectives: 

 

·       A heater chip that can simulate µProcessor operation will be utilized.   This device will be contained in a large array package that can be assembled onto a test board and tested to determine the impact.  

 

·      The test packaged device will be bench tested to determine power cycling parameters prior to inserting test parts into a temperature cycling chamber.

 

·       Two separate test chains for 1st and 2nd level testing will be designed into the test package and board.

 

·       The project will do side by side thermal cycling on the test boards. The test plan will have three devices per test card; one device with all heaters turned on; a second with edge heaters only; and the third with no mini-power cycling. This will enable results for all conditions to be taken on one board. The plan is to use a 30 oCΔT with power cycling.  The 30 oCΔT was a typical heat up cycle measured on a processor card during on and off operation.

 

Approach: 

Plan is to build Packaged heater chip to simulate microprocessor and test board. Then run power / Temp cycling simulaneously to map mini power cycles.

Key Participants: 
Celestica
Fujitsu
Kyzen
Oracle
Public