BGA pitch is moving steadily downward and high I/O BGAs are common at 1mm and 0.8mm pitch today and starting to appear at 0.65mm pitch. Consumer PCB’s (smart phone, tablet, etc.) have already moved to large I/O BGA’s at 0.5 and even 0.4mm pitch. This technology density is often supported by “Any Layer/Every Layer HDI PCB’s”. Generally the PCB’s used in Any Layer designs are very thin (typically 0.8mm thick or less). Participants in this project will determine the maximum PCB thickness that can be supported with “Any Layer” designs. The uniqueness of this project is the project is a new construction concept merging aspects of today’s high end telecom/computer designs with aspects of consumer PCB’s. There is no other similar project known to have been proposed or completed.
This project will use a new construction concept merging aspects of today’s high end telecom/computer designs with aspects of consumer PCB’s. There is no other similar project known to have been proposed or completed. There is interest in determining the maximum PCB thickness that can be supported with “Any Layer” designs.
A project with a test vehicle that is at least 10 layers thick to evaluate the capability of any layer technology for use in high performance computer boards or telecom industry board technology
HDI “stack” is current consumer technology and sub composite core is standard technology.
Connection of the HDI “stack” to the sub composite core “should” be only an extension of the same Cu sintered paste technology however there are issues that need to be answered to be able to apply this to real high reliability products.
What is the maximum current a single stack of sintered Cu paste vias can support?
What is the Pb-free survivability and IST thermal cycle reliability of a stack of microvias (10 layers?) in a thick composite board?
Are the sintered Cu paste vias susceptible to CAF?
Will the shear stresses of large high strain packages cause failures in the HDI stack of vias in ATC, or reflow cool down.
How stable is the sintered Cu paste material vs plated Cu?
Related to material stability, what is the electrical performance of series of sintered Cu paste vias?
These are just a few of the questions this project will address
The below picture is a schematic of the project proposal
Evaluate the performance and reliability of using "any layer" technology on thick boards capable of supporting the datacomm and military industry's
- Define and Design a test vehicle, 18X24 inches with 10 layer stacks of any layer technology
- Fabricate at multiple fabricators
- Assemble aqnd reflow
IST & Delam (PWB Interconnect Solutions)
Current carrying capability (Oracle)
CAF (PWB Interconnect Solutions or i3)