Future HDI

BGA pitch is moving steadily downward and high I/O BGAs are common at 1.0mm and 0.8mm pitch and starting to appear at 0.65mm pitch. Consumer PCB’s (smart phone, tablet, etc.) have already moved to large I/O BGA’s at 0.5mm and even 0.4mm pitch. This technology density is often supported by “Any Layer/Every Layer HDI PCB’s”. Generally the PCB’s used in Any Layer designs are very thin (typically 0.8mm thick or less). High density packages require 3 + stacks of microvias for routing (depending on how many I/O and design specifics) just to escape route these packages. It is inevitable that high I/O BGAs for high complexity products (Telecom, Server, etc.) will also trend downward in pitch, following the consumer trend.

 

Project stage: 
Project type: 
Lead company: 
Curtiss-Wright
If you are interested in participating in this project:
Members - Go to the "Subscribe Here" section to the right and select the "Subscribe to space" key.
Non Members - Go to the "Contact" section to the right and select the "Contact project facilitator" key.

 

Idea Information

Background: 

This project will use a new construction concept merging aspects of today’s high end telecom/computer designs with aspects of consumer PCB’s. There is no other similar project known to have been proposed or completed. There is interest in determining the maximum PCB thickness that can be supported with “Any Layer” designs.

 

A project with a test vehicle that is at least 10 layers thick to evaluate the capability of any layer technology for use in high performance computer boards or telecom industry board technology

 

Problem: 

HDI “stack” is current consumer technology and sub composite core is standard technology.

Connection of the HDI “stack” to the sub composite core “should” be only an extension of the same Cu sintered paste technology however there are issues that need to be answered to be able to apply this to real high reliability products.

 Questions like:

            What is the maximum current a single stack of sintered Cu paste vias can support?

            What is the Pb-free survivability and IST thermal cycle reliability of a stack of microvias (10 layers?) in a thick composite board?

            Are the sintered Cu paste vias susceptible to CAF?

            Will the shear stresses of large high strain packages cause failures in the HDI stack of vias in ATC, or reflow cool down.

             How stable is the sintered Cu paste material vs plated Cu?

            Related to material stability, what is the electrical performance of series of sintered Cu paste vias?

 These are just a few of the questions this project will address

 

The below picture is a schematic of the project proposal

 

Definition Information

Goals / Benefits: 

 

  • As a result of this project, members will have an understanding of via current carrying capacity. Trace current carrying capacity has been reported in the literature but there is very limited via current carrying capacity information available.

  • Conductive anodic filament (CAF) occurs in PCB’s when a Cu conductive filament forms between two adjacent conductors or plated through vias under an electrical bias. CAF can be a significant and potentially dangerous source of electrical failures in PCBs. The members will understand the impacts of CAF on sintered paste vias at pitches down to 0.35mm, and will be able to avoid this failure through smart design.

 

High level objectives: 

 

  • This project uses a new construction concept merging aspects of today’s high end telecom/computer designs with aspects of consumer PCB’s. There is no other similar project known to have been proposed or completed. There is interest in determining the maximum PCB thickness that can be supported with “Any Layer” designs. Figure “X” shows a proposed stack-up design for the TV.

  • The HDP membership will receive a report on the current carrying capacity of the technology, an IST thermal cycle analysis of the technology, a CAF analysis and possibly some electrical analysis.

  • The HDP membership will receive a complete ATC test evaluation of the technology. The design files will be made available on the HDP member webpage that will allow members to conduct their own evaluations of materials and vendors.

 

Approach: 

DOE/Test Plan

 IST & Delam (PWB Interconnect Solutions)

 Current carrying capability (Oracle)

 CAF (PWB Interconnect Solutions or i3)

 ATC (Nokia)

 TDR/SET2DIL (Polar)

 Flow Chart

 

Key Participants: 
Celestica
Ciena
Cisco
Flex
Fujitsu
IBM
Integral Technology
Isola Group
ITEQ
Oracle
Panasonic
Park Electrochemical
PWB Interconnect Solutions
Sanmina
TTM Technologies
Public