FCBGA Package Warpage

Most of the assembly industry is experiencing problems with the ever decreasing IC package thickness.  With denser packages (QFN's, Area Array's and Stacked Packages), the flatness of the packages and boards becomes more and more critical.
Warpage as a result of the thickness of the IC's used, can be a manufacturing night mare.  Defects such as open joints or very weak joints can be caused by short leads on the IC's combined with very flexible carriers.  This combination will most likely cause interconnections that will be poorly made or never made, resulting in a defect.
With the IC's becoming increasingly thinner, the silicon has less impact on resisting deformation of the package. The net result is that warpage will become an increasing problem in the future.

 
Project stage: 
Project type: 
Lead company: 
Plexus

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Idea Information

Background: 

With the introduction of area array packages, QFNs, stacked packages, etc. the flatness of packages and boards becomes critical.  Too much warpage and the short interconnections will poorly mate or never mate, resulting in either an open or very weak joint.  With the ICs used becoming increasingly thinner, the silicon has less impact on resisting deformation of the package. The net result is that warpage will become an increasing problem in the future. The aim of this project is to quantify the problem and to investigate possible commercially viable solutions to address the issue.

Problem: 
  1. Package/board Warpage increasing trends
    Driven by thinner package substrates and thinner die.
  2. Package/Board contacts getting smaller and closer thereby reducing ability to overcome increased Warpage.
  3. Solder Joint Quality Impact of increasing  Package and Warpage.
  4. With advent of  lead free soldering, the assembly temperatures have increased and  the warpage impact has exacerbated.

Definition Information

Approach: 
  • Planning Steps (9/12/12)  
  • Based on results from the above experimental evaluations, select the most promising mitigation path(s) to confirm their effectiveness by reflow soldering product packages on boards in manufacturing conditions

  • Assess various packages for the package termination-to-solder paste gap variation during the reflow process

  •  Develop a method(s) to control the termination-to-solder paste gap variation with temperature from room temperature to 250oC

  •  Brainstorm various paths of mitigating the solder joint defects caused by the variation of the gap during the reflow soldering process

  •  Experimentally evaluate the mitigation paths by dialing in the variation in this gap observed by the real time monitoring process into the method(s) developed to control the termination-to-solder paste gap

  •  Based on results from the above experimental evaluations, select the most promising mitigation path(s) to confirm their effectiveness by reflow soldering product packages on boards in manufacturing conditions

 

 

Key Participants: 
Celestica
Ciena
Cisco
Curtiss-Wright
Elite Material Co. EMC
Flex
Fujitsu
Hitachi Chemical
Huawei
IBM
Indium
Isola Group
Juniper
Keysight Technologies
Kyzen
Nihon Superior
NVIDIA
Oracle
Panasonic
Park Electrochemical
Plexus
Sanmina
Senju Comtek
Shengyi
TTM Technologies
Public