Electro-Chemical Migration 2

In our previous project Electro-Chemical Migration we found that a No Clean Flux, which is designed to leave a benign residue, can result in crevice and pitting corrosion. We also discovered the flux activators can remain on the board due to excessive flux or entrapment (ie,: Selective solder fixtures, Wicking into soldermask and Non solder mask defined pads).  We already knew that harsh environments subjects devices to high humidity.  This all means that Ions can be mobilized and cause corrosion on exposed copper features.  In this follow-on project we would like to develop a Test Method for determining Pitting / Crevice Corrosion capability of a Solder Flux. We then would submit the method to IPC Cleaning and Coating Committee for consideration of an additional test within J-STD 004 to evaluate flux potential to propagate Pitting / Crevice Corrosion capability of a Solder Flux on Cu and Sn and subsequently work with the IPC Committee on Cleanings and Coatings to implement our recommendations.

Project stage: 
Lead company: 
Kyzen

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Idea Information

Background: 
 
 
 
 
1. Various forms of corrosion and Electro Chemical Migration failures on products that pass the current cleanliness and corrosion resistance test protocols have demonstrated that these test procedures are not effective.
2. The failure mechanism is the same regardless what segment of the electronics industry the PCBA is used.
3. The current testing does not take into consideration various acceleration factors associated with no clean flux and product design features.
Problem: 
The current industry standard test protocols were originally developed to identify highly ionic contaminant levels (halides) after a cleaning process.  These test protocols are not completely effective at identifying Pitting / Crevice Corrosion from no-clean flux residues

Definition Information

Goals / Benefits: 

Develop and Validate a Test Method for testing the activity of liquid fluxes called out in J-STD-004B using Electrochemical Methods for their tendency to cause Pitting/Crevice Corrosion on Copper.

High level objectives: 

Define the unique conditions and design features under which contamination sources and environmental conditions can accelerate corrosion susceptibility on printed circuit boards

  • Known cleanliness levels
  • Sources of contamination
  • Solder mask defects
  • Current densities
  • Voltage gradient
  • Trace widths
  • Environmental conditions during test
Key Participants: 
Celestica
Dell
i3 Electronics
Keysight Technologies
Kyzen
MacDermid Enthone
Nihon Superior
NIST
Panasonic
RBP Chemical Technology
Public