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Through Silicon Vias

Idea/Definition Information
Summary: 

Through silicon vias (TSV) offer a potential solution to addressing some of the interconnect issues that impact the CPU-Memory latency bottle neck. This project  focuses on how TSVs can be adopted for this purpose and evaluates the challenges to applying this technology in future packaging solutions.  Possible exploration areas might include reliability of TSV interconnect, roadmapping, fabrication of high density TSV, and/or design tools.

If you are interested in this project and would like to subscribe to the project mailing list, please click here (members only) or email the project facilitator, Brian Smith - brians@hdpug.org.
 

Background: 

Through silicon via (TSV) technology is currently attracting significant attention in the industry. Already used extensively in high volume image sensors the technology is now seen as a potential solution to addressing some of the interconnect issues that impact the CPU-Memory latency bottle neck.  A range of fabrication solutions are now under development, that are providing designers with future options to interconnect on both sides of the silicon IC.  This helps to reduce interconnect lengths and potentially provides solutions for more efficient routing.

Problem: 

Designers of CPU chips are increasingly faced with the challenge of  accomodating sufficient on chip cache memory to meet the demands of latest generation processor cores. Packaging technology can ease this problem but only if the proximity of the off CPU memory chips are close enough to prevent the introduction of CPU to memory latency issues. The use of TSV technology can potentially address the proximity issue by allowing I/O between these two functional blocks by mounting the memory (stack)on the back of the CPU chip or alternatively face to face with a silicon interposer providing the interconnect medium between them.

To date TSVprocessing  is in its infancy and numerous challenges have to be overcome before it can be used to facilitate the potential solution discussed. The project is therefore intended to conduct a preliminary feasibility study on the suitability and maturity of TSV technology as a solution to the increaingly looming CPU to memory latency issue.

Approach: 

To date the exact nature of activities to be undertaken has yet to be decided. Possible exploration areas might include reliability of TSV interconnect, roadmapping, fabrication of high density TSV, and/or design tools. As the project is early in the ideas stage, suggestions are invited from members and non members to help scope and define the activities to be undertaken. 

A forum to share information on subjects related to TSV technology has been set up on the HDPUG website at the following link: http://hdpug.org/forum/131