Advanced QFN Evaluation

This project explored component footprint design and associated circuit board assembly processes for the latest generation of fine pitch QFN devices. The project conducted both post assembly yield assessments and longer term reliability testing (using accelerated thermal cycling techniques) to evaluate the impact of using different design and process parameters.

Project stage: 
Project type: 

Idea Information

Background: 

Quad Flat No (QFN) leads component packages are becoming increasingly popular, particularly for high density,small scale printed circuit board designs used in portable appliances. The packages offer low profile and space efficient solutions. However the absence of leads or solder balls combined with the very fine pitch of the terminations presents a new set of challenges for printed circuit assemblers.
 

Problem: 

The reliable use of fine pitch QFN components in PCB designs is dependent on advanced and high quality SMT assembly processes. Processes that are not fully optimized can lead to poor assembly yields and premature solder joint failure in the field. A particular challenge for the board assembler is to achieve consistent, defect free solder paste printing coupled with accurate placement of the components. With the introduction of increasingly fine pitch devices the demands intensify as the SMT process strives to achieve sufficient and well defined paste deposits without introducing the potential for open and short circuits. 

Members of HDP User Group identified a selection of newly developed fine pitch QFN packages with a range of pin counts. The aim of the project  was to attempt to optimize assembly processes to attach these devices and then to assess the reliability of the soldered parts.

Definition Information

Approach: 

The project undertook the following activities to achieve the objectives of the project:

  • Conducted a survey of and selected a range of advanced QFN components for evaluation in the project.
  • Identified relevant variables for SMT footprint design, solder mask design, solder past, solder paste stencil design and solder paste printing process
  • Generated design of experiment (DOE) matrix 
  • Designed,fabricated and assembled a batch of  test boards.
  • Conducted extensive yield analysis vs different  design variables on the test board.
  • Performed reliability testing  (accelerated thermal cycling)
  • Performed failure analysis 
  • Prepared conclusions and recommendations